The present invention generally relates to integrated circuits and more specifically to an improved method for forming high density integrated circuits containing complementary field effect transistors including guard rings.
Integrated circuits presently being used require power supply voltage greater than five volts. To achieve this, the turn on voltage of the field or parasitic thick oxide devices must be increased above the supply voltage. This is difficult to achieve in a high performance integrated process involving complementary MOS devices with polysilicon gates and ion implanted source and drains. One method to achieve higher field thresholds is by first increasing the size of the silicon dioxide steps on the chip resulting in larger final integrated chip size due to photoresist limitations, and secondly by increasing the P- and N-type background doping levels in the wafer, which degrades the device performance.
Another method uses guard rings or channel stops which are regions of very high impurity doping concentrations surrounding each N- and P-channel thin oxide MOS device. The high doping concentration increases the field threshold so high that the drain to source breakdown voltage of the thin oxide devices becomes the limiting factor of the IC power supply voltage. The rings generally require no extra processing steps because they are defined at the same time that the P and N channel devices are formed. This process is illustrated by U.S. Pat. No. 3,983,620. Separate processing steps for the guard rings and the source and drain is illustrated in U.S. Pat. No. 4,013,484. The guard rings must be separated from each surrounding device to prevent electrical shorts and adjacent rings must not touch. A ring separation of zero results in a process trade off of final device sheet resistivity versus field threshold and device breakdown voltage.
Local oxidation has been used in the formation of MOS devices as illustrated in U.S. Pat. Nos. 3,752,711 and 3,913,211. Since these patents deal generally with single polarity MOS devices, they do not treat the problems involved with forming two different conductivity type guard rings and their interaction. Similarly, the sequence of steps required to produce CMOS devices are not described therein.
Thus there exists a need for providing a method and an integrated circuit to form self-aligned guard rings in complementary integrated field effect transistor circuits to overcome the problems faced by prior art devices and techniques.